Semiconductor Device an Process for Fabricating the Same

ABSTRACT

A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

TECHNICAL FIELD

The present invention relates to a semiconductor device for allowingthin forming and high-speed operation and a process for fabricating thesame, and in particular to technology effectively applicable tomanufacturing technology of laminating a plurality of semiconductordevices sequentially to form a stacked semiconductor device.

BACKGROUND ART

Accompanied by trend toward multifunction and compactness of variouselectronic apparatuses, semiconductor devices incorporated in anelectronic apparatus leads to such a structure with a lot of built-incircuit elements even with compactness. As a method of improvingintegration density of a semiconductor device (integrated circuitdevice), three-dimensional stacked semiconductor device is known.

For example, such a structure of planning intensive integration with LSIchips having through-type electrodes over a plurality of stages stackedand secured on an interposer is proposed (for example, Patent Document 1and Non-Patent Document 1).

A three-dimensional device with first to third semiconductor substratesstacked to form an integrated circuit is known. In thisthree-dimensional device, an SOI substrate is used in the thirdsemiconductor device (for example, Patent Document 2).

As technology necessary for manufacturing a three-dimensional stackedLSI, there is technology of forming through-type electrodes in asemiconductor substrate. The current process of forming through-typeelectrodes in a silicon (Si) wafer still requires a lot of steps (forexample, Non-Patent Document 2).

[Patent Document 1]: Japanese Patent Laid-Open No. 2003-46057

[Patent Document 2]: Japanese Patent Laid-Open No. 2001-250913

[Non-Patent Document 1]: The Institute of Electrical Engineers of Japan,Research Reports of Materials Research Society, VOL. EFM-02-6, No. 1-8,P. 31-35

[Non-Patent Document 2]: Journal of the Surface Finishing Society ofJapan, VOL. 52, No. 7, 2001, P. 479-483

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

Conventional three-dimensional stacked semiconductor devices haveproblems as described below.

(1) In a multilayer structure of laminating LSI chips (for example,three chips and more), mainly an individual interposer is frequentlyprovided to implement lamination with that interposer. In this case, anindividual flip-chip technique is frequently adopted from a point ofview of characteristics. Flip-chip mounting will get costly. Inaddition, since an interposer is interposed individually, the inter-chipconnection path is lengthened, characteristics are deteriorated as well.

(2) Connection with bonding wire to replace a flip chip is applicable toaround three layers or four layers. However, increase in the number ofwires will require addition to the number of steps. Due to wires, theconnection path will be lengthened and increase in impedance will leadto deterioration in characteristics (high speed operation). Moreover,due to problems in handling, thin bear chips have a limitation forforming them thinly in its entirety.

(3) In order to increase the yield factor of a finished product, a finaltest must be carried out with a bear chip prior to mounting(lamination), but the final test with the bear chip and the final testwith so-called KGD (Known Good Die) are extremely costly due todifficulty in handling at the moment.

(4) Lamination in a plurality of sites on a chip is limited to two stepsat best, and even in this case, the connection path will be lengthenedto be apt to influence characteristics.

System in Package (SiP) is overwhelmingly less costly in development andshorter in development period compared with System on Chip (SoC) and istechnology to playing a role in sophisticated semiconductors in thefuture. SiP is used in cellular phones and digital cameras and the like,but further intensive integration is being demanded. Therefore, demandfor four-layer or five-layer lamination is expected to arise in the nearfuture, and moreover, combination thereof is assumed to demandflexibility.

An object of the present invention is to provide a stacked semiconductordevice capable of allowing short connection path between semiconductordevices and excellent in characteristics.

Another object of the present invention is to provide a thin stackedsemiconductor device allowing a various types of semiconductor devicesrespectively different in configuration to be laminated over a pluralityof steps.

An object of the present invention is to provide a process forfabricating a semiconductor device that enables a well productive andhighly reliable thin stacked semiconductor device to be fabricatedinexpensively.

An object of the present invention is to provide a process offabricating a stacked semiconductor device in which electronic partsincluding various types of semiconductor devices different inconfiguration can be easily laminated over a plurality of steps.

An object of the present invention is to provide a semiconductor devicethat allows a connection path to its outside to get short and sizethereof to get thin and fabrication to get inexpensive.

The above described as well as other objects and novel characteristicsof the present invention will become apparent with reference todescriptions as well as attached drawings hereof.

Means for solving the Problems

Summary of representative inventions among those disclosed herein willbe briefly described as follows.

(1) A stacked semiconductor device of the present invention has a firstsemiconductor device having outside electrode terminals on its lowersurface, a second semiconductor device electrically connected with theabove described first semiconductor device through joints and secured onthe above described first semiconductor device and a third semiconductordevice sequentially stacked and secured between the above describedfirst semiconductor device and second semiconductor device throughjoints, wherein

-   -   the above described first semiconductor device has:

a semiconductor substrate;

a multilayer wiring part including a plurality of circuit elementsformed at a first main surface side of the above described semiconductorsubstrate and wiring connected with the above described circuitelements;

a first insulating layer for covering the above described multilayerwiring part;

a second insulating layer for covering a second main surface to becomean opposite face against the first main surface of the above describedsemiconductor substrate;

a plurality of post electrodes formed on respective specified wiring ofthe above described multilayer wiring part to be exposed in a surface ofthe above described first insulating layer; and

a plurality of through-type electrodes provided to pierce through theabove described semiconductor substrate and the above described secondinsulating layer from specified depth of the above described multilayerwiring part, brought into contact to the above described semiconductorsubstrate through insulating film and connected with specified wiring ofthe above described multilayer wiring part respectively, and

-   -   the above described second semiconductor device has:

a semiconductor substrate;

a multilayer wiring part including a plurality of circuit elementsformed at a first main surface side of the above described semiconductorsubstrate and wiring connected with the above described circuitelements;

a first insulating layer for covering the above described multilayerwiring part;

a second insulating layer for covering a second main surface to becomean opposite face against the first main surface of the above describedsemiconductor substrate;

at least post electrodes formed on respective specified wiring of theabove described multilayer wiring part to be exposed in a surface of theabove described first insulating layer or

a plurality of through-type electrodes provided to pierce through theabove described semiconductor substrate and the above described secondinsulating layer from specified depth of the above described multilayerwiring part, brought into contact to the above described semiconductorsubstrate through insulating film and connected with specified wiring ofthe above described multilayer wiring part respectively, and

-   -   the above described third semiconductor device has:

a semiconductor substrate;

multilayer wiring part including a plurality of circuit elements formedat a first main surface side of the above described semiconductorsubstrate and wiring connected with the above described circuitelements;

a first insulating layer for covering the above described multilayerwiring part;

a second insulating layer for covering a second main surface to becomean opposite face against the first main surface of the above describedsemiconductor substrate;

a plurality of post electrodes formed on respective specified wiring ofthe above described multilayer wiring part to be exposed in a surface ofthe above described first insulating layer;

a plurality of through-type electrodes provided to pierce through theabove described semiconductor substrate and the above described secondinsulating layer from specified depth of the above described multilayerwiring part, brought into contact to the above described semiconductorsubstrate through insulating film and connected with specified wiring ofthe above described multilayer wiring part respectively, and

-   -   in the above described first semiconductor device, the above        described post electrodes or the above described through-type        electrodes come in the lower surface and the post electrodes or        the through-type electrodes in the lower surface is provided        with the above described outside electrode terminals;

the above described through-type electrodes or the above described postelectrodes in the lower surface of the above described thirdsemiconductor device are electrically connected with the above describedpost electrodes or the above described through-type electrodes in theupper surface of the above described first semiconductor device throughthe above described joints;

the above described post electrodes or the above described through-typeelectrodes in the lower surface of the above described secondsemiconductor device are electrically connected onto the above describedpost electrodes or the above described through-type electrodes in theupper surface of the above described third semiconductor device throughthe above described through-type electrodes.

Such a stacked semiconductor device has,

(a) a step of aligning, disposing and forming product forming part inplurality inclusive of specified circuit elements on a first mainsurface of a semiconductor substrate;

(b) a step of forming a multilayer wiring part by laminating and formingsequentially in a specified pattern wiring and insulating layers beingconnected electrically with the above described circuit elements;

(c) a step of forming, at a stage for forming the above describedmultilayer wiring part, a plurality of holes toward a second mainsurface to become an opposite face against the above described firstmain surface of the above described semiconductor substrate fromspecified depth of the above described multilayer wiring part havinginsulating film on their surfaces and of forming filling electrodes tofill those holes with conductive substance and be electrically connectedwith specified wiring of the above described multilayer wiring part;

(d) a step of forming post electrodes on respectively specified wiringof the above described multilayer wiring part;

(e) a step of forming, on the first main surface of the above describedsemiconductor substrate, a first insulating layer to cover the abovedescribed post electrodes;

(f) a step of removing the surface of the above described firstinsulating layer by specified thickness to expose the above describedpost electrodes;

(g) a step of removing the second main surface of the above describedsemiconductor substrate from its surface by specified thickness toexpose the above described filling electrodes to form through-typeelectrodes;

(h) a step of removing by etching the second main surface of the abovedescribed semiconductor substrate by specified thickness to cause theabove described through-type electrodes to protrude by specified length;

(i) a step of forming the second insulating layer of specified thicknesson the second main surface of the above described semiconductorsubstrate in a state of exposing forward ends of the above describedthrough-type electrodes; and

(j) a step of cutting the above described semiconductor substrateinclusive of the above described first and second insulating layers in alattice pattern to divide the above described product forming part; andhas

(k) a step of forming protruding electrodes at specified exposed endsamong the above described through-type electrodes and the abovedescribed post electrodes after the above described step (i) or afterthe above described step (j), wherein

through the above described step (a) to step (k), the above describedfirst semiconductor device and third semiconductor device are formed;

through selection of the above described step (a) to step (k), thesecond semiconductor device having only the above described through-typeelectrodes or only the above described post electrodes on the lowersurface is formed;

next, disposing the above described first semiconductor device so thatthe above described through-type electrodes or the above described postelectrodes come to the lower surface, the above described electrodes onthe lower surface are regarded as the above described outside electrodeterminals, and thereafter, the above described through-type electrodesor the above described post electrodes in the lower surface of the abovedescribed semiconductor device are overlapped and connected to the abovedescribed through-type electrodes or the above described post electrodesin the upper surface of the above described first semiconductor deviceby causing the above described protruding electrodes to undergo temporalheat processing, and

next, the above described through-type electrodes or the above describedpost electrodes in the lower surface of the above described secondsemiconductor device are overlapped and connected to the above describedthrough-type electrodes or the above described post electrodes in theupper surface of the above described third semiconductor device bycausing the above described protruding electrodes to undergo temporalheat processing to fabricate a stacked semiconductor device.

The above described second semiconductor device having only the abovedescribed through-type electrodes is formed through:

a step of aligning, disposing and forming product forming part inplurality inclusive of specified circuit elements on a first mainsurface of the above described semiconductor substrate;

a step of forming a multilayer wiring part by laminating and formingsequentially in a specified pattern wiring and insulating layers beingconnected electrically with the above described circuit elements;

a step of forming, at a stage for forming the above described multilayerwiring part, a plurality of holes toward a second main surface to becomean opposite face against the above described first main surface of theabove described semiconductor substrate from specified depth of theabove described multilayer wiring part having insulating film on theirsurfaces and of forming filling electrodes to fill those holes withconductive substance and be electrically connected with specified wiringof the above described multilayer wiring part;

a step of forming a first insulating layer on the first main surface ofthe above described semiconductor substrate;

a step of removing the second main surface of the above describedsemiconductor substrate from its surface by specified thickness toexpose the above described filling electrodes to form through-typeelectrodes;

a step of removing by etching the second main surface of the abovedescribed semiconductor substrate by specified thickness to cause theabove described through-type electrodes to protrude by specified length;

a step of forming the second insulating layer of specified thickness onthe second main surface of the above described semiconductor substrateto expose forward ends of the above described through-type electrodes;

a step of cutting the above described semiconductor substrate inclusiveof the above described first and second insulating layers in a latticepattern to divide the above described product forming part; and

a step of forming protruding electrodes at exposed portions of the abovedescribed through-type electrodes before or after the above describeddividing step.

The above described second semiconductor device having only the abovedescribed post electrodes is formed through:

a step of aligning, disposing and forming product forming part inplurality inclusive of specified circuit elements on a first mainsurface of a semiconductor substrate;

a step of forming a multilayer wiring part by laminating and formingsequentially in a specified pattern wiring and insulating layers beingconnected electrically with the above described circuit elements;

a step of forming post electrodes on respectively specified wiring ofthe above described multilayer wiring part;

a step of forming, on the first main surface of the above describedsemiconductor substrate, a first insulating layer to cover the abovedescribed post electrodes;

a step of removing the surface of the above described first insulatinglayer by specified thickness to expose the above described postelectrodes;

a step of removing the second main surface of the above describedsemiconductor substrate from its surface by specified thickness to makethe above described semiconductor substrate thin;

a step of forming the second insulating layer of specified thickness onthe second main surface of the above described semiconductor substrate;

a step of cutting the above described semiconductor substrate inclusiveof the above described first and second insulating layers in a latticepattern to divide the above described product forming part; and

a step of forming protruding electrodes at exposed portions of the abovedescribed post electrodes before or after the above described dividingstep.

(2) The above described configuration (1) is characterized in that aplurality of second semiconductor devices smaller than the abovedescribed first semiconductor device are disposed and secured inparallel on the above described first semiconductor device.

ADVANTAGES OF THE INVENTION

Effects derived by representative inventions among those disclosedherein will be briefly described as follows.

According to means in the item (1), (a) the first, the third and thesecond semiconductor devices, in fabrication thereof, the firstinsulating layers are formed at the first main surface sides of thesemiconductor substrates and thereafter the second main surfaces of thesemiconductor substrates undergo thickness removal by a specifiedamount, but since the above described first insulating layers act asstrength member, the semiconductor substrates can be made thin to alevel of around 5 to 50 μm. In addition, since thickness of theinsulating layers can also be made thin to a level of around 20 to 100μm, in such a state that thickness of the protruding electrodes is notconsidered, respective semiconductor devices can be made to havethickness of, for example, around 40 to 100 μm so that thinning of thestacked semiconductor device can be attained. If a value of the lowerlimit is taken for thickness of the semiconductor substrates andinsulating layers, further thinning can be planned.

(b) In the first, the third and the second semiconductor devices, inconnecting the semiconductor device at the lower stage side with thesemiconductor device at the upper stage side, connection is carried outin utilization of post electrodes to become columnar provided bypiercing through the first insulating layer and through-type electrodesto become columnar provided by piercing through the semiconductorsubstrate, and therefore, the current pathway will get short to makereduction in inductance attainable and to make electrical property ofthe stacked semiconductor device good. The post electrodes andthrough-type electrodes provided in the first insulating layer andsemiconductor substrate are short with length thereof being around 5 to50 μm, and will become sufficiently short compared with length of notless than several hundred micrometers of a bonding wire by means of wireconnection. Thereby, high speed operation of the stacked semiconductordevice will become feasible.

(c) There is a constraint that the through-type electrodes provided inthe semiconductor substrate is formed in a region apart from the regionwhere circuit elements are formed, and nevertheless the disposinglocations for wiring regions and the like can be selected comparativelyfreely. The disposing location for the post electrodes connected withspecified wiring of the multilayer wiring part can be determinedcomparatively freely by deploying wiring. Therefore, by selectinglocations to provide the through-type electrodes and the postelectrodes, improvement in integration density in the two-dimensionaldirection can be planned.

(d) The stacked semiconductor device of the present invention willbecome capable of electrically connecting the semiconductor device atthe lower stage side with the semiconductor device at the upper stageside without using any interposer. Consequently, reduction in the numberof assembling parts items can be planned and thinning of the stackedsemiconductor device can be planned. Use of interposer will lengthenconnecting path (current pathway) between semiconductor chips or betweensemiconductor devices, but no use of interposer will enable the currentpathway to get short so that improvement in electrical property can beplanned.

(e) In fabricating the stacked semiconductor device of the presentinvention, the first, the third and the second semiconductor devices arefabricated in use of the semiconductor wafers in fabrication thereof,which together with insulating layers are cut at the final stage tofabricate the first, the third and the second semiconductor devices.Accordingly, since required processing other than stacking and securingthe first, the third and the second semiconductor devices is carried outon a wafer level, handling performance is good throughout the steps andwasteful work will get less. Consequently, reduction in production costscan be planned.

(2) According to the above described structure (1), a plurality ofsecond semiconductor devices smaller than the above described firstsemiconductor device are disposed and secured in parallel on the abovedescribed first semiconductor device, and therefore further improvementin integration can be planned.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of a stacked semiconductor devicebeing Embodiment 1 of the present invention;

FIG. 2 is a schematic perspective view showing an appearance of theabove described stacked semiconductor device;

FIG. 3 is a schematic bottom view of the above described stackedsemiconductor device;

FIG. 4 is a flow chart showing a process for fabricating a stackedsemiconductor device of Embodiment 1;

FIG. 5 is a schematic sectional view showing filling electrodes havingbeen formed in a semiconductor substrate with ICs and the like havingbeen formed in the fabricating process;

FIG. 6 is an enlarged schematic sectional view of a part of asemiconductor substrate showing the lower portion of the above describedfilling electrode and multilayer wiring part;

FIG. 7 is an enlarged schematic sectional view of a part of the abovedescribed filling electrode, multilayer wiring part and the like;

FIG. 8 is a schematic sectional view of the above describedsemiconductor substrate showing a state with a post electrodes and afirst insulating layer having been formed on a first major surface;

FIG. 9 is an enlarged schematic sectional view of a part of asemiconductor substrate with the above described post electrode andfirst insulating layer having been formed;

FIG. 10 is an enlarged schematic sectional view showing a part of afilling electrode structure being a variation of Embodiment 1;

FIG. 11 is an enlarged schematic sectional view showing a part of afilling electrode structure being another variation of Embodiment 1;

FIG. 12 is a schematic sectional view of a part of a semiconductorsubstrate showing a state of the surface of the above described firstinsulating layer being removed by a specified thickness to expose thepost electrode;

FIG. 13 is a schematic sectional view of the above describedsemiconductor substrate showing a state of the second main surface beingremoved by a specified thickness to expose the filling electrode tobecome a through-type electrode;

FIG. 14 is a schematic sectional view showing a state of a forward endof the through-type electrode projected by etching the second mainsurface of the above described semiconductor substrate;

FIG. 15 is a schematic sectional view of the above describedsemiconductor substrate showing a state of the second insulating layerformed so as to expose the forward tip of the through-type electrode onthe second main surface;

FIG. 16 is a schematic sectional view showing a state with protrudingelectrodes having been formed on the forward tips of the above describedthrough-type electrodes as well as post electrodes;

FIG. 17 is a schematic sectional view showing a semiconductor substrate(semiconductor wafer) with the above described semiconductor substrateto come to the lower surface side and the first insulating layer to cometo the upper surface side;

FIG. 18 is a schematic plan view showing stacked semiconductor devicesaccording to Embodiment 1 having been disposed and housed in a tray;

FIG. 19 shows schematic views showing three types of semiconductordevices (first semiconductor device, third semiconductor device andsecond semiconductor device) having been formed in Embodiment 1respectively in a laminated order in a separated fashion;

FIG. 20 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 1 having been mounted on adaughter board;

FIG. 21 is a schematic sectional view of a stacked semiconductor devicebeing Embodiment 2 of the present invention;

FIG. 22 shows schematic sectional views of a stacked semiconductordevice with two-layer lamination being Embodiment 3 of the presentinvention;

FIG. 23 shows sectional views of respective steps showing a part of aprocess for fabricating a stacked semiconductor device being Embodiment4 of the present invention;

FIG. 24 shows sectional views of respective steps showing a part of aprocess for fabricating a stacked semiconductor device being Embodiment4 of the present invention;

FIG. 25 shows sectional views of respective steps showing a part of aprocess for fabricating a stacked semiconductor device being Embodiment5 of the present invention;

FIG. 26 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 6 of the present inventionhaving been mounted on a daughter board;

FIG. 27 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 7 of the present inventionhaving been mounted on a daughter board;

FIG. 28 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 8 of the present inventionhaving been mounted on a daughter board; and

FIG. 29 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 9 of the present inventionhaving been mounted on a daughter board.

DESCRIPTION OF SYMBOLS

1 . . . stacked semiconductor device, 2 . . . first semiconductordevice, 3 . . . second semiconductor device, 4 . . . third semiconductordevice, 5 . . . outside electrode terminal, 6 a, 6 b, 6 c . . .semiconductor substrate, 7 a, 7 b, 7 c . . . multilayer wiring part, 8a, 8 b, 8 c . . . first insulating layer, 9 a, 9 b, 9 c . . . postelectrode, 10 a, 10 b, 10 c . . . protruding electrode, 11 a, 11 b, 11 c. . . second insulating layer, 12 . . . filling electrode, 12 a, 12 b,12 c . . . through-type electrode, 13 a, 13 b, 13 c . . . protrudingelectrode, 21 . . . first well, 22 . . . second well, 23 . . . sourceregion, 24 . . . drain region, 25 . . . insulating gate film, 26 . . .gate electrode, 27, 28 . . . electrode, 29 . . . thick oxide film, 30 .. . insulating layer, 31 . . . wiring layer (wiring), 32 . . . electrodepad, 33 . . . hole, 34 . . . insulating film, 40 . . . tray, 41 . . .housing depression, 45 . . . daughter board, 46 . . . bump electrode,50, 51, 80, 81 . . . underfill layer, 60, 70 . . . metal plate, 61, 71 .. . insulating hole.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail belowwith reference to drawings. The like reference characters and numeralsdesignate the parts having the same functions throughout the figures fordescribing embodiments of the present invention and repeateddescriptions thereof will be omitted.

EMBODIMENT 1

FIG. 1 to FIG. 20 relate to a stacked semiconductor device beingEmbodiment 1 of the present invention. FIG. 1 to FIG. 3 relate tostructures of the stacked semiconductor device, FIG. 4 to FIG. 19 relateto fabrication of the stacked semiconductor device and FIG. 20 is adrawing showing a state of mounting the stacked semiconductor device.

A stacked semiconductor device 1 fabricated subject to a process offabricating the present invention consists of, as shown in FIG. 2, arectangular first semiconductor device 2 to become a lower stage, amiddle stage third semiconductor device 4 stacked and secured on theupper surface of this first semiconductor device 2 and an upper stagesecond semiconductor device 3 stacked and secured on the upper surfaceof this third semiconductor device 4. In the stacked semiconductordevice 1 of Embodiment 1, the first, the second and the thirdsemiconductor devices 2, 3 and 4 have the same planar sizes and arestacked in a corresponding fashion. FIG. 3 is a drawing showing a bottomview of the stacked semiconductor device 1 which has external electrodeterminals 5 formed with protruding electrodes provided on the lowersurface of the first semiconductor device.

In the first, the second and the third semiconductor devices 2, 3 and 4,respective semiconductor devices are different in presence or absence ofthrough-type electrodes and post electrodes at the stacked and securedsurface side and in presence or absence of joints for bringing thethrough-type electrodes and the post electrodes into connection, andtherefore names of respective parts are the corresponding names whilesymbols for the first semiconductor device 2 are provided with “a” atthe end of numerals, symbols for the second semiconductor device 3 areprovided with “b” at the end of numerals and symbols for the thirdsemiconductor device 4 are provided with “c” at the end of numerals fordescription. The protruding electrodes (bump electrodes) provided atexposed ends of the through-type electrode and the post electrodeundergo temporal heating processing to form the above described joints.

The first semiconductor device 2 has a rectangular semiconductorsubstrate 6 a. The semiconductor substrate 6 a is, for example, made ofsilicon (Si) and a multilayer wiring part 7 a is formed on a first mainsurface (a surface where circuits such as IC and the like are formed, orthe upper surface in FIG. 1) side thereof and the multilayer wiring part7 a is provided with a first insulating layer 8 a made of insulatingresin thereon. The insulating layer is generally formed of resin, forexample, insulating resin such as polyimide resin, epoxy resin and thelike, to be used for fabricating a semiconductor device. Thesemiconductor substrate 6 a has thickness of, for example, around 20 μm.The semiconductor substrate 6 a may have thickness of around 6 to 50 μm.The insulating layer will become strength member when to fabricate asemiconductor device and is comparatively thick to have, for example,thickness of around 50 μm. The insulating layer may have thickness ofaround 20 to 100 μm.

There provided are post electrodes 9 a made of columnar copper (Cu)piercing through the first insulating layer 8 a to be electricallyconnected to specified wiring of the multilayer wiring part 7 a. Thepost electrodes 9 a are exposed on the surface of the first insulatinglayer 8 a. The exposed portions of the post electrodes 9 a are providedwith protruding electrodes 10 a. The protruding electrodes 10 a are bumpelectrodes made of, for example, solder balls, gold balls, copper ballssubject to plating with gold on their surfaces and the like.

On the first main surface of the semiconductor substrate 6 a activeelements such as transistors, diodes and the like in various types ofstructures and passive elements such as resistance elements, capacitorelements, inductor elements and the like are formed in accordance withnecessity. The post electrodes 9 a have diameter of around 10 μm andthickness of 50 μm. The post electrodes 9 a may have diameter of around10 to 50 μm and thickness of around 20 to 100 μm. The protrudingelectrodes 10 a are formed of balls having diameter of, for example,around 60 μm in size prior to connection and have thickness of around 40μm. Balls having diameter of around 40 to 80 μm may be used to form theprotruding electrodes 10 a.

The second main surface (the bottom surface in FIG. 1) to become therear side of the above described first main surface of the semiconductorsubstrate 6 a is provided with a second insulating layer 11 a made ofinsulating resin. The second insulating layer 11 a is formed of, forexample, polyimide resin. The second insulating layer 11 a has thicknessof, for example, around several micrometers to 10 μm that will at leastsecure electrical insulation. The embodiment hereof has thickness ofaround 5 μm.

Through-type electrodes 12 a are provided to pierce through thesemiconductor substrate 6 a as well as the second insulating layer 11 afrom specified depth of the multilayer wiring part 7 a. Thosethrough-type electrodes 12 a are electrically connected to specifiedwiring of the multilayer wiring part 7 a. The through-type electrodes 12a are formed of columnar copper plating. The through-type electrodes 12a have diameter of, for example, around 10 μm. The through-typeelectrodes 12 a may have diameter of around several micrometers to 30μm. The through-type electrodes 12 a, as to be described below, contactsthe semiconductor substrate 6 a through insulating film that comesbetween the semiconductor substrate 6 a and the circumference surface ofthe through-type electrodes 12 a so that they are electricallyindependent from the semiconductor substrate 6 a.

The through-type electrodes 12 a are exposed on the surface of thesecond insulating layer 11 a. The exposed portions of those through-typeelectrodes 12 a are provided with protruding electrodes 13 a. Theprotruding electrodes 13 a are ball bump electrodes made of, forexample, gold balls, copper balls subject to plating with gold on theirsurfaces, solder balls and the like. The protruding electrodes 13 a arealso balls in size similar to protruding electrodes 10 a. The protrudingelectrodes may be formed by plating or printing (screen printing). Inthat case, the protruding electrodes may have thickness of around 10 μm.

The stacked semiconductor device 1 of Embodiment 1 is structured sothat, in any of the first, second and third semiconductor devices 2, 3,4, the first insulating layers 8 a, 8 b, 8 c come to the top andsemiconductor substrates 6 a, 6 b, 6 c come to the bottom.

The middle stage third semiconductor device 4 is different from thefirst semiconductor device 2 in the pattern of the post electrodes 9 cand through-type electrodes 12 c, but is structured substantially thesame as the first semiconductor device 2 in the other portions. Thethird semiconductor device 4 is not provided with any protrudingelectrode. The reason thereof is to use, for connection, protrudingelectrodes of semiconductor device of the counter party to be stackedwhen to be stacked and secured. However, such a process may be adoptedthat protruding electrodes are provided in the post electrodes 9 c andthe through-type electrodes 12 c so that the protruding electrodes areconnected each other for carrying out stacking and securing.

The third semiconductor device 4 in the middle stage is provided with amultilayer wiring part 7 c and a first insulating layer 8 c on the firstmain surface (upper surface) of a semiconductor substrate 6 c and thesecond main surface is provided with an insulating layer 11 c. The firstinsulating layer 8 c is provided with a plurality of post electrodes 9 cto be electrically connected to specified wiring of the multilayerwiring part 7 c. And there are a plurality of through-type electrodes 12c piercing through the second insulating layer 11 c from thesemiconductor substrate 6 c to be electrically connected to specifiedwiring of the multilayer wiring part 7 c. Those through-type electrodes12 c have insulating surface on their circumference and are insulatedand separated from the semiconductor substrate 6 c.

The through-type electrodes 12 c on the lower surface side of the thirdsemiconductor device 4 in the middle stage and the post electrodes 9 aon the upper surface side of the first semiconductor device 2 in thelower stage are respectively facing each other and are electricallyconnected through the protruding electrodes 10 a. The protrudingelectrodes 10 a will undergo temporal heat processing to become jointsso as to connect the connecting portions. That connection will cause thethird semiconductor device 4 to be stacked and secured on the firstsemiconductor device 2.

The second semiconductor device 3 in the upper stage is structured likethe first semiconductor device 2 except that the upper surface is notprovided with any post electrode. That is, the second semiconductordevice 3 is structured to have a multilayer wiring part 7 b as well as afirst insulating layer 8 b on a first main surface (upper surface) of asemiconductor substrate 6 b and a second insulating layer 11 b on asecond main surface. Through-type electrodes 12 b are provided to piercethrough the semiconductor substrate 6 b and the second insulating layer11 b. The through-type electrodes 12 b are electrically connected tospecified wiring of the multilayer wiring part 7 b. The exposed portionsof those through-type electrodes 12 b on the surface of the secondinsulating layer 11 b are provided with protruding electrodes 13 b.

The through-type electrodes 12 b on the bottom surface side of the thirdsemiconductor device 3 in the upper stage and the post electrodes 9 c onthe upper surface side of the third semiconductor device 4 in the middlestage are respectively facing each other and are electrically connectedthrough the protruding electrodes 13 b. That connection will cause thesecond semiconductor device 3 to be stacked and secured on the thirdsemiconductor device 4.

The protruding electrodes 10 a bringing the first semiconductor device 2and the third semiconductor device 4 into connection will become jointsand the protruding electrodes 13 b bringing the third semiconductordevice 4 and the second semiconductor device 3 into connection willbecome joints. When the protruding electrodes are formed of balls indiameter of around 60 μm, the protruding electrodes having thickness ofaround 40 μm can be formed. When the above described joints are formedof protruding electrodes, the joints will have thickness of around 20μm. In the case where protruding electrodes are formed in postelectrodes and through-type electrodes, it is advisable that desiredplating film is formed in advance onto a surface where through-typeelectrodes and protruding electrodes are exposed when it is difficult toform the protruding electrode directly.

Respective semiconductor devices can be caused to have thicknesses ofaround 40 to 100 μm by respectively selecting specified sizes from thesize range shown in the embodiment, and therefore, the stackedsemiconductor device 1 stacked and secured in three stages will havethickness of around 200 to 380 μm in case of ball bump electrodes and,in case of protruding electrodes by means of printing, of around 150 to330 μm that is extremely thin. Height of that stacked semiconductordevice 1 will vary in accordance with size (thickness) of the ball bumpelectrodes and the protruding electrodes by means of printing.

In the stacked semiconductor device 1 fabricated by stacking andsecuring, the protruding electrodes 13 a provided at the bottom surfaceof the semiconductor substrate 6 a will become outside electrodeterminals 5. In case of using the first semiconductor device 2 todispose the first insulating layer 8 a at the bottom surface, theprotruding electrodes 10 a will become the outside electrode terminals5.

Next, a process for fabricating the stacked semiconductor device 1 ofEmbodiment 1 hereof will be described. FIG. 4 is a flow chart showing aprocess for fabricating the stacked semiconductor device 1. That flowchart constitutes respective flowcharts respectively consisting ofstages from a step 11 (S11) to a step 21 (S21) to fabricate a firstsemiconductor device 2 in the bottom stage, a third semiconductor device4 in the middle stage and a second semiconductor device 3 in the upperstage and a stage of a step S22 to stack and secure the semiconductordevices in the bottom stage, the middle stage and the upper stage.

The first semiconductor device 2 in the lower stage is formed throughrespective steps of forming circuit elements onto a semiconductorsubstrate (Step S11), forming filling electrodes as well as electrodepads at a stage of forming multilayer wiring part (Step S12), formingpost electrodes (Step S13), forming a first insulating layer (to embedpost electrodes: Step S14), removing surface of the first insulatinglayer (to expose post electrodes: Step S15), removing the substratesurface (to form through-type electrodes: Step S16), etching thesubstrate surface (to protrude through-type electrodes: Step S17),forming a second insulating layer (to expose the through-type electrode:Step S18), forming protruding electrodes (through-type electrodes andpost electrodes: Step S19), separation (into individual pieces: StepS20) and performing a characteristics test (Step S21).

The third semiconductor device 4 in the middle stage is fabricatedthrough the same stages as in the stages for fabricating the abovedescribed first semiconductor device 2 in the lower stage, and howeverthe through-type electrodes 12 c provided to the lower side are formedin a pattern to face the post electrodes 9 a on the upper surface of thefirst semiconductor device 2 in the lower stage.

Since no post electrode is formed in the second semiconductor device 3in the upper stage, the stage of Step S13 will become unnecessary. Sinceno post electrode is provided, a first insulating layer is formed inStep S14 while the surface of the first insulating layer is removed inStep S15 and consideration on post electrodes will be no longerrequired.

The first, third and second semiconductors 2, 4 and 3 formed in thestage of Step S21 are sequentially stacked in the stacking and securingstage (Step S22) and are stacked and secured through, for example, areflow oven to fabricate the stacked semiconductor device 1 shown inFIG. 1 to FIG. 3.

Any semiconductor device of the stacked semiconductor device 1 inEmbodiment 1 is a semiconductor device in use of a silicon substrate.However, semiconductor devices in use of compound semiconductor such asGaAs, InP or the like and semiconductor devices in use of siliconsubstrates may be brought into combination. In such a case, circuitelements suitable for material are formed in the semiconductor portions.

Next, fabrication of the first semiconductor device 2 in the lower stagewill be described. FIG. 5 is a schematic sectional view showing fillingelectrodes having been formed in a semiconductor substrate (siliconsubstrate) with ICs and the like having been already formed infabricating the stacked semiconductor device 1.

In fabricating a semiconductor device, a wide area semiconductor waferis prepared and thereafter unit circuits inclusive of specified circuitelements are formed on the first main surface of that wafer. Those unitcircuits are formed on the first main surface of that wafer while beingaligned and disposed in a lattice. Thereafter, subject to respectiveprocesses, lastly cut and separated in a checked fashion, a great numberof semiconductor elements (semiconductor chips) are formed. Thatrectangular shape region (portion) to form that unit circuit will bereferred to as product forming part herein. Between a product formingpart and a product forming part, there positioned is a scribe line toundergo dividing or a dicing region to undergo cutting. Lastly, cuttingtakes place in that dicing region. In FIG. 5 and forward, only a singleproduct forming part will be shown. Accordingly, as far as there is noproblem, a major part of names will be taken from names used in a stateof a finished product for descriptions.

As shown in FIG. 5, after a semiconductor substrate 6 a having thicknessof several hundreds micrometers is prepared, circuits (circuit elements)are formed on a first main surface of that semiconductor substrate 6 a(Step S11). A multilayer wiring part 7 a is formed on the first mainsurface of the semiconductor substrate 6 a. At the stage for formingthat multilayer wiring part 7 a, holes are formed on the first mainsurface of the semiconductor substrate 6 a. Thereafter, the surface ofthe hole undergo oxidization and subsequently a plating film is filledand formed inside the hole. By filling with that plating film, fillingelectrodes 12 are formed. The holes have, for example, diameter ofaround several micrometers to 30 μm and depths of around 5 to 50 μm. Inthe embodiments, they have, for example, diameter of around 10 μm and adepth of 30 μm. In this embodiment, at the point of time when asemiconductor device is formed, the semiconductor substrate 6 a is madethin to make the first semiconductor device 2 thin. Therefore, in caseof enhancing the thin structure further, the above described holes maybe made further shallower so as to make processing the holes easier. Theplating film is formed of, for example, copper. The process for formingthe filling electrodes 12 may be the other process. For example, such aprocess may be employed for forming the filling electrodes 12 thatsubjects to filling the interior of the holes with electricallyconductive particles sprayed in an ink jet system and thereafterundergoing hardening by means of heat processing. For example, tungsten,titanium, nickel, aluminum or alloy thereof may be used for filling withCVD (chemical vapor depositing).

FIG. 6 is an enlarged schematic sectional view of a part of asemiconductor substrate showing the lower layer portion of the abovedescribed filling electrode and multilayer wiring part. A semiconductor6 a is a substrate of a first electrically conductive type, and a firstwell 21 of a second electrically conductive type and a second well 22 ofthe first electrically conductive type are formed in a surface layerportion on the first main surface side. In the first well 21, a sourceregion 23, a drain region 24 and an insulating gate film 25 are formedand a gate electrode 26 is formed on the insulating gate film 25 to forma field effective transistor (FET). Electrodes 27 and 28 are formed onthe surfaces of the first and the second wells 22 respectively. A thickoxide film 29 is selectively provided on the first main surface of thesemiconductor substrate 6 a.

FIG. 7 is an enlarged schematic sectional view of a part of the abovedescribed filling electrode, multilayer wiring part and the like. Asshown in FIG. 7, on the first main surface of the semiconductorsubstrate 6 a, the insulating layers 30 and the wiring layers (wiring)31 are alternately laminated and formed in a specified pattern to form amultilayer wiring part 7 a. The wiring layer in the uppermost layerforms an electrode pad 32. A part of that electrode pad 32 is exposed.Post electrodes 9 a will be formed in the exposed portions. Therefore,the exposed portions become holes having diameter of around 10 μm. FIG.6 shows the insulating layer 30 and wiring layers (wiring) 31 in thelowest layer of the multilayer wiring part 7 a.

At the stage for forming the multilayer wiring part 7 a, the abovedescribed filling electrode 12 is formed in the semiconductor substrate6 a. In the embodiment, at the stage for having formed the circuitelements and formed the thick oxide film 29, the above described hole 33is formed on the first main surface side of the semiconductor substrate6 a with photolithography technology and photo etching for normal use.Thereafter, oxidation processing is carried out to form an insulatingfilm 34 on the surface of the hole 33. Moreover, copper plating iscarried out to fill the hole 33 with a copper plating film to form thefilling electrode 12. For example, the filling electrode 12 will havediameter of around 10 μm and a depth of around 30 μm. Thereby, thefilling electrode and the electrode pad are formed (Step S12). Thefilling electrode 12 will be electrically insulated due to contact withthe semiconductor substrate 6 a through the insulating film 34.

The above described filling electrode 12 may be formed by sprayingelectrically conductive liquid in an inkjet system to embed the hole 33.In that case, after spaying, the filled electrically conductive liquidundergoes hardening processing (baking). The other metal, for example,tungsten, titanium, nickel, aluminum or alloy thereof may be used forfilling with CVD (chemical vapor depositing) so as to form a CVD film.

As described above, since the insulating film 34 is interposed betweenthe filling electrode 12 and the semiconductor substrate 6 a, thefilling electrode 12 will be electrically separated (independent) fromthe semiconductor substrate 6 a.

At the time when the insulating layers 30 and the wiring layers (wiring)31 are alternately laminated and formed sequentially in a specifiedpattern to form a multilayer wiring part 7 a on the first main surfaceof the semiconductor substrate 6 a, the filling electrode 12 iselectrically connected with specified wiring of the multilayer wiringpart 7 a.

Next, as shown in FIG. 8, specified positions on the first main surfaceof the semiconductor substrate 6 a undergo plating to form a pluralityof columnar post electrodes 9 a (Step S13). As for those post electrodes9 a, likewise the above described filling electrodes 12, copper,tungsten, titanium, nickel, aluminum or alloy thereof may be used toform a CVD film.

Next, a first insulating layer 8 a is formed on the first main surfaceof the semiconductor substrate 6 a (Step S14). The post electrodes 9 aare covered with the first insulating layer 8 a. Insulating organicresin such as epoxy resin, polyimide resin and the like is used for thefirst insulating layer 8 a. The first insulating layer 8 a is formedwith, for example, transfer molding or squeegee printing.

FIG. 9 is an exemplary enlarged schematic sectional view of a part of asemiconductor substrate with the above described post electrode andfirst insulating layer having been formed thereon. A post electrode 9 ais formed on the upper surface of the electrode pad 32 and the postelectrode 9 a is covered with the first insulating layer 8 a. FIG. 9depicts the post electrode 9 a to be formed thinner than the electrodepad 32 by a large margin. This assumes direct use of a process forfabricating an IC and the like having an electrode pad to be connectedwith wires. In order to connect an IC and the like with electricallyconductive wires, the electrode pad is shaped rectangular with a sidehaving length of around 80 to 100 μm. Therefore, in the embodiment, thepost electrode 9 a is provided on that electrode pad 32. Use of theelectrode pad 32 by means of an established IC process as wiring portionfor forming the post electrode 9 a is also one technique. But, thepresent invention will not be limited thereto, but the post electrode 9a may be formed in a wiring portion with small area.

FIG. 10 and FIG. 11 are examples (variations) with the post electrode 9a formed on the electrode pad 32 to have nearly the same diameter as theelectrode pad 32.

The structure of FIG. 10 is an example where the filling electrode 12has been formed at a comparatively early stage for forming themultilayer wiring part 7 a. After having formed the first layer and thesecond layer of insulating layers 30 on the first surface side of thesemiconductor substrate 6 a, the hole 33 is formed in those two layersof the insulating layer 30 and semiconductor substrate 6 a andsubsequently the hole 33 is filled with a plating film to form thefilling electrode 12.

The structure in FIG. 11 is an example of a filling electrode 12 thathas been formed at a stage of a comparatively later period for formingthe multilayer wiring part 7 a. After having formed a first layer to afourth layer of insulating layers 30 on the first surface side of thesemiconductor substrate 6 a, a hole 33 is formed in those four layers ofthe insulating layer 30 and the semiconductor substrate 6 a, andsubsequently the hole 33 is filled with a plating film to form a fillingelectrode 12.

As shown in FIG. 7, FIG. 10 and FIG. 11, the hole 33 can be formed in afreely selective fashion at a desired stage for forming the multilayerwiring part 7 a so as to enable electrical connection with specifiedwiring (wiring layer 31) of the multilayer wiring part 7 a. Sincestructures in FIG. 7 and FIG. 9 are already described in detail in FIG.9 and FIG. 10, a part of symbols will be omitted.

Next, as shown in FIG. 12, the surface of the first insulating layer 8 ais removed by a specified thickness (Step S15). For example, the surfaceof the first insulating layer 8 a is ground so as to expose the forwardend of the post electrode 9 a. If the quantity of grinding gets larger,the thickness of the post electrode 9 a gets shorter and the thicknessof the first insulating layer 8 a gets thinner as well. In the presentembodiment, after making the semiconductor substrate 6 a thin to bedescribed later, since the first insulating layer 8 a is used as astrength member for supporting the semiconductor substrate 6 a, thethickness of the first insulating layer 8 a, for example, is set toaround 50 μm. In the case where there is no problem in handling thesemiconductor substrate 6 a in terms of strength, the first insulatinglayer 8 a may be made further thinner. This will lead to thinning of thefirst semiconductor device 2 and thinning of the stacked semiconductordevice 1.

Next, as shown in FIG. 13, the second main surface of the semiconductorsubstrate 6 a is ground so as to expose the forward ends of the fillingelectrodes 12 and to form the through-type electrodes 12 and with thefilling electrodes 12 (Step S16). Thereby, the semiconductor substrate 6a will have thickness of around 25 μm. Even if the semiconductorsubstrate 6 a gets thin like this, the first insulating layer 8 a isthick and thereby the semiconductor substrate 6 a can prevent damagessuch as cracking at the time of handling or breakage from taking place.

Next, as shown in FIG. 14, the second main surface side of thesemiconductor substrate 6 a undergoes etching for a specified thickness.Etching is carried out with wet etching with etching solution of ahydrofluoric acid system and the through-type electrodes 12 a do notundergo etching. Thereby, the forward ends of the through-typeelectrodes 12 a will be protruded by around 5 μm from the semiconductorsubstrate 6 a having thickness of around 20 μm.

Next, as shown in FIG. 15, a second insulating layer 11 a is formed onthe silicon surface at the second main surface side of the semiconductorsubstrate 6 a. At that time, the second insulating layer 11 a is formedso as to expose the forward ends of the through-type electrodes 12 a(Step S18). The second insulating layer 11 a may be formed with, forexample, spinner application, and squeegee printing or film-typesubstance is pasted by heat processing and pasted with insulatingadhesive for forming. Thickness of the second insulating layer 11 a isset to thickness that enables electrical insulation to be planned atleast. In forming this second insulating layer 11 a, it can be formed byapplying insulating material that is hydrophobic to through-typeelectrodes 12 a being Cu and is hydrophilic to Si. That is, providingthe second insulating layer 11 a so as to reach approximate height ofprotrusion of the through-type electrodes 12 a, the forward ends of thethrough-type electrodes 12 a are exposed from the second insulatinglayer 11 a.

Next, as shown in FIG. 16, protruding electrodes 10 a and 13 a areformed at the forward ends of the post electrodes 9 a to be exposed onthe front side of the second insulating layer 11 a and the forward endof the through-type electrodes 12 a to be exposed on the second mainsurface side of the semiconductor substrate 6 a (Step S19). Theprotruding electrodes 10 a and 13 a are bump electrodes made of, forexample, solder balls, gold balls, copper balls having undergone goldplating on their surfaces and the like or by screen printing andheating. When it is difficult to form protruding electrodes directly tothe post electrodes and the through-type electrodes, it is advisable toform a plating film on the exposed surfaces of the post electrodes andthe through-type electrodes in advance for making connection well.

Next, the semiconductor wafer is divided in a checked fashion to formindividual pieces (Step S20). The drawing has been described not in astate of a semiconductor wafer but in a state of a single productforming part. Therefore, the first semiconductor device 2 that has beendivided and formed will have sectional structure shown in FIG. 16 aswell. In embodiments, the bump electrodes have been formed andthereafter undergone processing to form individual pieces but the bumpelectrodes may be formed after processing to form individual pieces.

In FIG. 16, the semiconductor substrate 6 a is disposed to the uppersurface side and the first insulating layer 8 a is disposed to the lowersurface side, and, in FIG. 17, the semiconductor substrate 6 a isdisposed to the lower surface side and the first insulating layer isdisposed to the upper surface side. The first semiconductor device 2 isused as a semiconductor device disposed at the lowest stage at the timeof stacking and securing, but in the case where the protrudingelectrodes 10 a are used as shown in FIG. 16 as outside electrodeterminals at that time, or as shown in FIG. 17, the protrudingelectrodes 13 a will be used as outside electrode terminals.

Next, after forming an individual chip, that is, the first semiconductordevice 2, a normal test (electrical property test) is carried out. Atthat time, as shown in FIG. 18, respective chips (first semiconductordevices 2) are housed in housing depressions 41 provided in a matrixstate on the upper surface of the tray 40. Since the upper surface andthe rear surface of the first semiconductor device 2 are respectivelycovered with insulating material, the test can be carried outsimultaneously as well as in parallel with a probe test. Products havingbeen found to be defective are excluded. In FIG. 18, the protrudingelectrodes 13 a of the first semiconductor devices 2 are displayedschematically. Use of such a tray 40 allows arrangement of products inan array state to make collective testing possible and to make handlingof the products easier to improve test efficiency.

In general, in fabricating a semiconductor device, an electricalproperty test of products (circuits) of respective product forming partsof the semiconductor wafer is performed in a state of a semiconductorwafer. That is, a probe nail is brought into contact with an electrodeexposed in respective product forming parts of a semiconductor wafer toperform an electrical property test, and also in the present embodiment,a same probe test may be performed prior to dividing processing so as toperform measurement and a test on quality of products (circuits) ofrespective product forming parts. The first semiconductor device 2 isfabricated by the above described process.

The third semiconductor device 4 stacked and secured on the firstsemiconductor device 2 is fabricated by the same steps as in the firstsemiconductor device 2, that is, respective steps of Step S11 to StepS21 shown in FIG. 4. At that time, the third semiconductor device 4 canbe used in a state as shown in FIG. 16 or FIG. 17, that is, so that theprotruding electrodes 10 a are located on the lower surface or theprotruding electrodes 13 a are located on the lower surface. Selectionthereof is free, but it is necessary to form the protruding electrodes10 a or the protruding electrodes 13 a on the lower surface of the thirdsemiconductor device 4 so as to be connectable to the protrudingelectrodes 10 a or the protruding electrodes 13 a on the upper surfaceof the first semiconductor device 2. Since the third semiconductordevice to become the middle stage is provided with the bump electrodesengaged in connection in the first semiconductor device 2 at the lowerstage side and the second semiconductor device 3 at the upper stageside, the bump electrodes do not have to be provided with intentionally.Therefore, the third semiconductor device 4 may be stacked and securedas shown in the middle stage in FIG. 19 in such a state that no bumpelectrode is provided. Moreover, the third semiconductor device 4 at themiddle stage may be provided with the protruding electrodes either onthe upper surface or on the lower surface. In that case, thesemiconductor device does not have to be provided in advance withprotruding electrodes intentionally on its surface that faces thesurface provided with protruding electrodes, and the protrudingelectrodes provided in the third semiconductor device 4 at the middlestage act as joints.

The second semiconductor device 3 stacked and secured on the uppersurface of the third semiconductor device 4 is structured to form eitherthe through-type electrodes 12 a or the post electrodes 9 a infabricating the above described first semiconductor device 2. That is,since it will come to the uppermost stage, no outside electrode terminalis necessary on its upper surface.

In Embodiment 1 hereof, as shown in FIG. 4, the second semiconductordevice 3 will be described with an example without forming any postelectrode but with forming through-type electrodes 12 a. In fabricatingthe second semiconductor device 3, circuit element forming onto thesemiconductor substrate (Step S11) is the same but only fillingelectrodes at the stage for forming a multilayer wiring part are formedin Step S12. Thereafter the step goes forward to Step S14. In this StepS14, only first insulating layer 8 a is formed. Since no post electrodeis present in Step S15, relationship with post electrodes does not haveto be considered, but thickness of the first insulating layer 8 a issecured. Subsequent Step S16, Step S17 and Step S18 will be the sameprocessing. In Step S19, protruding electrodes 13 b are formed only atthe forward ends of the through-type electrodes 12 a. Subject todivision in Step S20 and a property test in Step S21, the secondsemiconductor device 3 shown in the uppermost stage in FIG. 19 isformed.

FIG. 19 is a drawing where three types of semiconductor devices (thefirst semiconductor device 2, the third semiconductor device 4 and thesecond semiconductor device 3) having been formed in Embodiment 1 areshown in an order of lamination and in a separated fashion. Those threeparties of the semiconductor devices 2, 4 and 3 are aligned so that theconnecting portions overlap and the protruding electrodes undergoheating and melting temporally through the furnace body and are joined.As for connection in the connecting portions, heat may be locallyapplied to the connecting portions so as to carry out connection. InEmbodiment 1, the connecting portions between the first semiconductordevice 2 and the third semiconductor device 4 are protruding electrodes10 a and the through-type electrodes 12 c while the connecting portionsbetween the third semiconductor device 4 and the second semiconductordevice 3 are the post electrodes 9 c and the protruding electrodes 13 b.They form a joint. Thus stacked and secured, the stacked semiconductordevice 1 shown in FIG. 1 to FIG. 3 can be fabricated. The protrudingelectrodes 13 a on the lower surface of the first semiconductor device 2at the lowest stage will become outside electrode terminals 5 (see FIG.1).

FIG. 20 is a schematic sectional view showing amounting state of thestacked semiconductor device 1 fabricated with the process forfabricating the stacked semiconductor device of Embodiment 1 hereof. Thestacked semiconductor device 1 is mounted on the upper surface of adaughter board 45 made of a multilayer wiring substrate. The daughterboard 45 has a plurality of bump electrodes 46 on its lower surface andon its upper surface there formed is a land which is are not shown inthe drawing, though. The disposing pattern of the outside electrodeterminals 5 of the stacked semiconductor device 1 corresponds to thedisposing pattern of the above described land. Accordingly, reflow ofthe outside electrode terminals 5 enables the stacked semiconductordevice 1 to be mounted onto the daughter board 45.

In Embodiment 1 hereof, fabrication technologies on the stackedsemiconductor device 1 have been described, and in consideration as asingle product, the first semiconductor device 2 and the thirdsemiconductor device 4 can be shipped respectively as a single product.According to the present invention, those semiconductor devices 2 and 4are characterized by causing the through-type electrodes and the postelectrodes to become electrodes respectively to protrude from the upperand lower surfaces of the semiconductor devices.

Embodiment 1 hereof gives rise to following effects.

(1) In fabricating the stacked semiconductor device 1 formed by stackingand securing the first, second and third semiconductor devices 2, 3 and4, the first insulating layers 8 a, 8 b and 8 c are formed at the firstmain surface sides of the semiconductor substrates 6 a, 6 b and 6 c ofthe respective semiconductor devices 2, 3 and 4 and thereafter thesecond main surfaces of the semiconductor substrates 6 a, 6 b and 6 cundergo thickness removal by a specified amount, but since the abovedescribed first insulating layers 8 a, 8 b and 8 c act as strengthmembers, the semiconductor substrates 6 a, 6 b and 6 c can be made thinto a level of around 5 to 50 μm. Thicknesses of the insulating layers 8a, 8 b and 8 c can also be made thin to a level of around 20 to 100 μm.Therefore, in the stacked semiconductor device 1 stacked and secured,the bump electrodes will have heights (thicknesses) of around 200 to 380μm so that the protruding electrodes by means of printing can be madethin to have heights (thicknesses) of around 150 to 330 μm. Therefore,thinning of the semiconductor devices (integrated circuit devices:three-dimensional integrated circuit devices) of the multilayer stackedstructure can be planned.

(2) In the first, the third and the second stacked semiconductordevices, in connecting the semiconductor device at the lower stage sidewith the semiconductor device at the upper stage side, connection iscarried out in utilization of post electrodes to become columnarprovided by piercing through the first insulating layer and through-typeelectrodes to become columnar provided by piercing through thesemiconductor substrate, and therefore, the current pathway will getshort to make reduction in inductance attainable and to make electricalproperty of the stacked semiconductor device 1 good. The post electrodesand through-type electrodes provided in the first insulating layer andsemiconductor substrate are short with length (thickness) thereof beingaround 20 to 100 μm or 5 to 50 μm, and will become sufficiently shortcompared with length of not less than several hundred micrometers of abonding wire by means of wire connection. Thereby, high speed operationof the stacked semiconductor device 1 will become feasible.

(3) There is a constraint that the through-type electrodes provided inthe semiconductor substrate is formed in a region apart from the regionwhere circuit elements are formed, and nevertheless disposing locationsfor wiring regions and the like can be selected comparatively freely.The disposing location for the post electrodes connected with specifiedwiring of the multilayer wiring part can be determined comparativelyfreely by deploying wiring. Therefore, selecting locations to providethe through-type electrodes and the post electrodes, improvement inintegration density in the two-dimensional direction can be planned.

(4) The stacked semiconductor device 1 of Embodiment 1 hereof willbecome capable of electrically connecting the semiconductor device atthe lower stage side with the semiconductor device at the upper stageside without using any interposer. Consequently, reduction in the numberof assembling parts items can be planned and thinning of the stackedsemiconductor device can be planned. Use of interposer will lengthenconnecting path (current pathway) between semiconductor chips or betweensemiconductor devices, but no use of interposer will enable the currentpathway to get short so that improvement in electrical property can beplanned.

(5) In fabricating the stacked semiconductor device 1 of Embodiment 1hereof, the first, the third and the second semiconductor devices 2, 4,and 3 are fabricated in use of the semiconductor substrates 6 a, 6 c and6 b, and the semiconductor substrates 6 a, 6 c and 6 b together with theinsulating layers are cut at the final stage to fabricate the first, thethird and the second semiconductor devices 2, 4 and 3. Accordingly,since required processing other than stacking and securing the first,the third and the second semiconductor devices 2, 4 and 3 is carried outon a wafer level, handling performance is good throughout the steps andwasteful work will get less. Consequently, reduction in production costscan be planned.

(6) In fabricating the stacked semiconductor device 1 of Embodiment 1hereof, at the stage before the three semiconductor devices 2, 4 and 3are stacked and secured, all processing is implemented on a wafer level,and therefore, the process is simplified so as to increase productivityand reduction in fabrication costs of the stacked semiconductor device 1can be attained.

(7) According to the process for fabricating the stacked semiconductordevice of Embodiment 1 hereof, just planning correspondence of theconnecting portions of the semiconductor devices to be verticallyoverlapped enables the semiconductor devices to be stacked into furtherabundance of layers, and therefore the stacked semiconductor device 1undergoing further sophisticated integration can be fabricated.

(8) In the stacked semiconductor device 1 of Embodiment 1 hereof, in thestructure thereof, as in the above described article (7), except aconstraint of planning correspondence of the connecting portions of thesemiconductor devices to be vertically overlapped, the circuits formedin respective semiconductor devices can be designed freely. That is,taking the above described constraint as one of designing tools, thestacked semiconductor device 1 can be designed as if it were one chip.In the current designing tools, only such a designing tool is present inassumption of one chip LSI (corresponding to each semiconductor deviceof Embodiment 1 hereof).

Under the circumstances, in designing System in Package, simulating whatkind of circuit is appropriate for each semiconductor device subject todetermination based on performance, costs, simplicity of the test andthe like and allocating respective semiconductor devices based on thatsimulation outcome, the stacked semiconductor device 1 excellent inelectric property and high speed operation performance can be fabricatedin compact, thin and inexpensive fashion.

(9) The first semiconductor device 2 and the third semiconductor device4 being single product are structured to cause the through-typeelectrodes and the post electrodes, that will become electrodesrespectively, to protrude from the upper and the lower surface of thesemiconductor devices. Due to the above described articles (1) to (3)and articles (5) to (6) deriving from this characteristic and due tosimplification of the process, thinning, high speed operation andimprovement in density of integration in the two-dimensional directioncan be planned even for the single semiconductor device, and reductionin cost for fabrication thereof can be planned due to fabrication in astate of a wafer.

EMBODIMENT 2

FIG. 21 is a schematic sectional view of a stacked semiconductor devicebeing Embodiment 2 of the present invention. Embodiment 2 hereof isconfigured, in the stacked semiconductor device 1 of Embodiment 1, tofill a gap between the first semiconductor device 2 and the thirdsemiconductor device 4 as well as a gap between the third semiconductordevice 4 and the second semiconductor device 3 with insulating resin toform underfill layers 50 and 51. With those underfill layers 50 and 51,the gaps are filled and therefore short defects due to incorporation offoreign substance and the like can be prevented. Polyimide resin, forexample, as insulating resin is caused to fill the gaps in a vacuumatmosphere and thereafter is hardened subject to bake processing.

EMBODIMENT 3

FIG. 22( a) and FIG. 22( b) show schematic sectional views of a stackedsemiconductor device 1 of a two-stage stacked and secured type beingEmbodiment 3 of the present invention. In both of FIG. 22( a) and FIG.22( b), the semiconductor substrates 6 a and 6 b disposed upper and thefirst insulating layers 8 a and 8 b disposed lower have been stacked andsecured. In any of them, the protruding electrodes 10 a on the lowersurface of the first semiconductor device 2 will become outsideelectrode terminals 5. The protruding electrodes 13 a on the uppersurface of the first semiconductor device 2 will become joints so thatthe second semiconductor device 3 is stacked and secured. That is, theprotruding electrodes 13 a attached to the through-type electrodes 12 aat the upper surface side of the first semiconductor device 2 arestructured to be connected to the post electrodes 9 b in the lowersurface of the second semiconductor device 3.

In FIG. 22( a), the second semiconductor device 3 is structured so thatno electrode is exposed at its upper surface side, that is, isstructured so that the semiconductor substrate 6 b is provided with nothrough-type electrode 12 b.

In contrast, in FIG. 22( b), the semiconductor substrate 6 b at theupper surface side of the second semiconductor device 3 is provided withthrough-type electrodes 12 b. The through-type electrodes 12 b arestructured to have diameter of the same level as the through-typeelectrode 12 b in case of Embodiment 1 and thick through-type electrodes12 b shown at the both end sides in the drawing. The thick through-typeelectrodes 12 b have diameter of the same level as the electrode pad asdescribed with reference to FIG. 10, and, for example, can be connectedwith wires. That is, they can be connected with the pads of a daughterboard with electrically conductive wires.

In contrast, a plurality of thin through-type electrodes 12 b as thosein Embodiment 1 are configured, for example, to be connected to one endof the electrode plate 55 connected to the ground of the daughter board.According to the present embodiment, due to a structure to expose thethrough-type electrodes 12 b in the upper surface of the secondsemiconductor device 3 at the upper stage, the degree of allowance forcircuit designing (implementation designing) inclusive of the daughterboard increases.

In the present embodiment, active elements (active parts) such as chipresistors, chip capacitors, chip inductor and the like may be mounted atthe upper surface side of the second semiconductor device 3. Electrodesof respective active elements are electrically connected with thethrough-type electrodes 12 b. Such configuration will increase theintegration level.

EMBODIMENT 4

FIG. 23 and FIG. 24 are drawings related to a process for fabricatingstacked semiconductor device being Embodiment 4 of the presentinvention. In Embodiment 4 hereof, substantially likewise the case ofEmbodiment 1, the stacked semiconductor device 1 is fabricated throughstages of Step S11 to Step S22, but the first semiconductor device 2 isconnected with the third semiconductor device 4 with inter-metal jointby means of ultrasonic oscillation without using any protrudingelectrode. Therefore, a portion thereof is different in fabrication.

As shown in FIG. 23( a), in fabricating the first semiconductor device2, after the post electrodes 9 a provided at the first main surface sideof the semiconductor substrate 6 a are covered with the first insulatinglayer 8 a, primary hardening processing to implement processing ofhardening resin insufficiently is implemented at the time of hardeningprocessing (cure) of the first insulating layer 8 a.

Next, as shown in FIG. 23( b), the surface of the first insulating layer8 a is ground by specified thickness and is removed so as to expose thepost electrode 9 a.

As shown in FIG. 23( c), such secondary hardening processing (cure) thatthe first insulating layer 8 a accompanies hardening contraction isimplemented to expose forward ends of the post electrodes 9 a on thesurface of the first insulating layer 8 a. For example, length ofprotrusion is around 10 μm. That protrusion length is length requiredfor implementing inter-metal joint by means of ultrasonic oscillationeffectively.

Next, the first semiconductor device 2, the third semiconductor device 4and the second semiconductor device 3 undergo positioning and arestacked. FIG. 24( a) shows an order of lamination, and is a drawing inwhich the first semiconductor device 2 is positioned in the lowestlayer, the third semiconductor device 4 is positioned thereabove, andthe second semiconductor device 3 is positioned apart thereon.

There, nothing is shown in particular in the drawing, but the thirdsemiconductor device 4 undergoes positioning and is disposed on thefirst semiconductor device 2, and the post electrodes 9 a made of Cu onthe upper surface of the first semiconductor device 2 are rubbed to thethrough-type electrodes 12 c made of Cu on the lower surface of thethird semiconductor device 4 by relatively applying ultrasonicoscillation so that rubbed surfaces between the post electrodes 9 a andthrough-type electrodes 12 c are connected by inter-metal joint (metaljoint). Thereafter, the second semiconductor device 3 is stacked andsecured on the third semiconductor device 4 by the same process as inEmbodiment 1 to fabricate the stacked semiconductor device 1 as shown inFIG. 24( b).

In this example, the gap between the first semiconductor device 2 andthe third semiconductor device 4 is filled with an insulating underfilllayer 50 and the gap between the third semiconductor device 4 and thesecond semiconductor device 3 is filled with an insulating underfilllayer 51.

The present embodiment is characterized in that, when the firstsemiconductor device 2 and the third semiconductor device 4 are stackedand secured, no protruding electrode is used, and therefore furtherthinning processing can be planned.

EMBODIMENT 5

FIG. 25( a) and FIG. 25( b) show sectional views of respective stepsshowing a part of a process for fabricating a stacked semiconductordevice being Embodiment 5 of the present invention. Embodiment 5 hereofis an example of stacking and securing with metal joint likewiseEmbodiment 4. In this example, after the third semiconductor device 4 isstacked and secured onto the first semiconductor device 2 by metaljoint, the third semiconductor device 4 is stacked and secured onto thethird semiconductor device 4 by metal joint. In the present embodiment,likewise Embodiment 4, at the time of fabricating the firstsemiconductor device 2 and the third semiconductor device 4, the forwardends of the post electrodes 9 a and 9 c of the first semiconductordevice 2 and the third semiconductor device 4 are caused to protrudefrom the surface of the first insulating layers 8 a and 8 c by around 10μm.

FIG. 25( a) shows an order of lamination, and is a drawing in which thefirst semiconductor device 2 is positioned in the lowest layer, thethird semiconductor device 4 is positioned thereabove, and the secondsemiconductor device 3 is positioned apart thereon.

There, nothing is shown in particular in the drawing, but the thirdsemiconductor device 4 undergoes positioning and is disposed on thefirst semiconductor device 2, and the post electrodes 9 a made of Cu onthe upper surface of the first semiconductor device 2 are rubbed to thethrough-type electrodes 12 c made of Cu on the lower surface of thethird semiconductor device 4 by relatively applying ultrasonicoscillation so that rubbed surfaces between the post electrodes 9 a andthrough-type electrodes 12 c are connected by inter-metal joint (metaljoint).

Next, likewise, nothing is shown in particular in the drawing, but thesecond semiconductor device 3 undergoes positioning and is disposed onthe third semiconductor device 4, and the post electrodes 9 c made of Cuon the upper surface of the third semiconductor device 4 are rubbed tothe through-type electrodes 12 b made of Cu on the lower surface of thesecond semiconductor device 3 by relatively applying ultrasonicoscillation so that rubbed surfaces between the post electrodes 9 c andthrough-type electrodes 12 b are connected by inter-metal joint (metaljoint).

In this example, the gap between the first semiconductor device 2 andthe third semiconductor device 4 is filled with an insulating underfilllayer 50 and the gap between the third semiconductor device 4 and thesecond semiconductor device is filled with an insulating underfill layer51.

The present embodiment is characterized in that, when the firstsemiconductor device 2 and the third semiconductor device 4 are stackedand secured and the third semiconductor device 4 and the secondsemiconductor device 3 are stacked and secured, no protruding electrodeis used, and therefore further thinning processing can be planned.

EMBODIMENT 6

FIG. 26 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 6 of the present inventionhaving been mounted in a daughter board. In Embodiment 6 hereof, thefirst semiconductor device 2, the second semiconductor device 3 and thethird semiconductor device 4 of the stacked semiconductor device 1 arestacked and secured in such a state that any of the semiconductorsubstrates 6 a, 6 b and 6 c is located at the upper surface side and thefirst insulating layers 8 a, 8 b and 8 c are located at the lowersurface side. And the first semiconductor device 2 is mounted onto thedaughter board 45 by connecting the protruding electrodes 10 a of thefirst semiconductor device 2 with lands not shown in the drawing of thedaughter board 45.

EMBODIMENT 7

FIG. 27 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 7 of the present inventionhaving been mounted in a daughter board. The present embodiment is amixed type with the first semiconductor device 2 and the secondsemiconductor device 3 of the stacked semiconductor device 1 beingstacked and secured in such a state that the semiconductor substrates 6a and 6 b are located at the upper surface side and the first insulatinglayers 8 a and 8 b are located at the lower surface side, and for thethird semiconductor device 4, being stacked and secured in such a statethat the semiconductor substrate 6 c is located at the lower surfaceside and the first insulating layer 8 c is located at the upper surfaceside. And the first semiconductor device 2 is mounted onto the daughterboard 45 by connecting the protruding electrodes 10 a of the firstsemiconductor device 2 with lands not shown in the drawing of thedaughter board 45.

EMBODIMENT 8

FIG. 28 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 8 of the present inventionhaving been mounted on a daughter board. Embodiment 8 hereof isstructured so that a plurality of semiconductor devices 4A and 4B beingthe middle stage third semiconductor devices 4 smaller than the firstsemiconductor device 2 are disposed and secured in parallel on the firstsemiconductor device 2, and semiconductor devices 3A and 3B to becomethe second semiconductor devices 3 are stacked and secured respectivelyon those semiconductor devices 4A and 4B. That is, in Embodiment 8hereof, a great number of middle stage third semiconductor devices 4 aredisposed in parallel in plurality on the first semiconductor device 2with the largest area, and, moreover, the upper stage secondsemiconductor devices 3 are stacked and secured respectively on thosethird semiconductor devices 4. The middle stage third semiconductordevice may consist of a plurality of stages to be stacked and securedbetween the lower stage first semiconductor device and the upper stagesecond semiconductor device so as to further improve integration level.

In Embodiment 8 hereof, among the above described first to thirdsemiconductor devices, the above described semiconductor substrate ofone semiconductor device is a silicon substrate and the above describedsemiconductor substrate of another semiconductor device is a compoundsemiconductor substrate. And circuit elements suitable for respectivesemiconductor substrates are formed. For example, the semiconductorsubstrate 6 a of the first semiconductor device 2 is a silicon substrateand the semiconductor substrate 6 cA of the semiconductor device 3A is acompound semiconductor (for example, a GaAs substrate). Thesemiconductors at the middle stage and the upper stage, almost all thesymbols will be omitted. However, in necessity for descriptions, themiddle stage third semiconductor devices 4A and 4B will be provided withA or B at the ends for depiction. The upper stage second semiconductordevices 3A and 3B will be provided with A or B at the ends fordepiction.

In Embodiment 8, semiconductor devices are designated for all parts tobe incorporated in the stacked semiconductor device 1, but the otherelectronic parts may be stacked and secured. For example, chip partssuch as resistors, capacitors and the like, MEMS (Micro electroMechanical System), biochips and the like may be stacked and secured.Silicon substrates as semiconductor substrates and compoundsemiconductor substrates as semiconductor substrate may be present morein number.

According to Embodiment 8 hereof, further intensive integration isattained.

EMBODIMENT 9

FIG. 29 is a schematic sectional view of a state showing the stackedsemiconductor device according to Embodiment 9 of the present inventionhaving been mounted on a daughter board. Embodiment 9 hereof is anexample in which, in Embodiment 8, a metal plate 60 is sandwichedbetween the first semiconductor device 2 and the semiconductor device 4Bthereabove and a metal plate 70 is sandwiched between the semiconductordevice 4B and the semiconductor device 3B. Circuitwise, for example, themetal plate 70 is configured to be given the ground potential and themetal plate 60 is configured to be given the power supply potential(reference potential) such as Vcc and the like.

That is, the metal plate 60 having insulating holes 61 is presentbetween the first semiconductor device 2 and the semiconductor device4B. In the portion of the insulating holes 61, the through-typeelectrodes 12 a on the upper surface of the first semiconductor device 2are electrically connected with the post electrodes 9 cB on the lowersurface of the semiconductor device 4B through the protruding electrodes13 a and the protruding electrodes 10 cB in a state without contactingthe metal plate 60.

The through-type electrodes 12 a of the first semiconductor device 2 andthe semiconductor device 4B to face the metal plate 60 are electricallyconnected with the post electrodes 9 cB on the lower surface of thesemiconductor device 4B through the protruding electrodes 13 a and theprotruding electrodes 10 cB. Since inter position of the metal plate 60lengthens the distance between the through-type electrodes 12 a and thepost electrodes 9 cB, the protruding electrodes 13 a and the protrudingelectrodes 10 cB used for connection in the portion of the insulatingholes 61 are made larger than the protruding electrodes 13 a and theprotruding electrodes 10 cB connected to the metal plate 60.

In addition, the metal plate 70 having insulating holes 71 is presentbetween the semiconductor device 4B and the semiconductor device 3B aswell. In the portion of the insulating holes 71, the through-typeelectrodes 12 bB on the upper surface of the semiconductor device 4B areelectrically connected with the post electrodes 9 bB on the lowersurface of the semiconductor device 3B through the protruding electrodes13 cB and the protruding electrodes 10 bB in a state without contactingthe metal plate 70. The through-type electrodes 12 cB of thesemiconductor device 4B and the post electrodes 9 bB of thesemiconductor device 3B to face the metal plate 70 are brought intoelectrical connection through the protruding electrodes 13 cB and theprotruding electrodes 10 bB. Since interposition of the metal plate 70lengthens the distance between the through-type electrodes 12 cB and thepost electrodes 9 bB, the protruding electrodes 13 cB and the protrudingelectrodes 10 bB used for connection in the portion of the insulatingholes 71 are made larger than the protruding electrodes 13 cB and theprotruding electrodes 10 bB connected to the metal plate 70.

The gap between the first semiconductor device 2 and the semiconductordevice 4B is filled with an underfill layer 80 and the gap between thesemiconductor device 4B and the semiconductor device 3B is filled withan underfill layer 81.

According to Embodiment 9 hereof, presence of the metal plate 70 giventhe ground potential and the metal plate 60 given the power supplypotential (reference potential) such as Vcc and the like stabilizes thepower supply as well as the ground of the stacked semiconductor device1, and consequently stabilizes operations and can derive good electricalproperty.

So far, the invention attained by the present inventor has beendescribed in particular based on embodiments, and nevertheless thepresent invention will not be limited to the above describedembodiments, but it goes without saying that various changes can be madewithout departing the gist thereof. In the embodiments, the postelectrodes have been formed with plating but may be formed with studbumps. Stud bumping is a system of connecting a gold wire with anelectrode pad with a thermo compression method (ball bonding method) toform a nail head, and thereafter cutting the wire in the base portion ofthat nail head to form protruding electrodes which are stacked in manystages.

INDUSTRIAL APPLICABILITY

As described above, the stacked semiconductor device related to thepresent invention can be used as a thin three-dimensional integratedcircuit device suitable for high speed operation. In addition, thestacked semiconductor device related to the present invention allowsallocation of respective semiconductor devices in the stackedsemiconductor device subject to simulation based on determination onperformance, costs, simplicity of the test and the like in designingSystem in Package. Therefore, according to the present invention, thestacked semiconductor device being excellent in electric property andhigh speed operation performance and to become compact and thin andinexpensive can be provided.

1. A stacked semiconductor device consisting of a first semiconductordevice having outside electrode terminals on its lower surface, a secondsemiconductor device electrically connected with said firstsemiconductor device and secured on said first semiconductor device,characterized in that: said first semiconductor device has: asemiconductor substrate; a multilayer wiring part including a pluralityof circuit elements formed at a first main surface side of saidsemiconductor substrate and wiring connected with said circuit elements;a first insulating layer for covering said multilayer wiring part; asecond insulating layer for covering a second main surface to become anopposite face against the first main surface of said semiconductorsubstrate; a plurality of post electrodes formed on respective specifiedwiring of said multilayer wiring part to be exposed in a surface of saidfirst insulating layer; a plurality of through-type electrodes providedto pierce through said semiconductor substrate and said secondinsulating layer from specified depth of said multilayer wiring part,brought into contact to said semiconductor substrate through aninsulating film and connected with specified wiring of said multilayerwiring part respectively; and said outside electrode terminals connectedto said through-type electrodes; said second semiconductor device has: asemiconductor substrate; a multilayer wiring part including a pluralityof circuit elements formed at a first main surface side of saidsemiconductor substrate and wiring connected with said circuit elements;a first insulating layer for covering said multilayer wiring part; asecond insulating layer for covering a second main surface to become anopposite face against the first main surface of said semiconductorsubstrate; at least post electrodes formed on respective specifiedwiring of said multilayer wiring part to be exposed in a surface of saidfirst insulating layer or a plurality of through-type electrodesprovided to pierce through said semiconductor substrate and said secondinsulating layer from specified depth of said multilayer wiring part,brought into contact to said semiconductor substrate through aninsulating film and connected with specified wiring of said multilayerwiring part respectively, and in said first semiconductor device, saidpost electrodes or said through-type electrodes come in a lower surfaceand said post electrodes or said through-type electrodes in the lowersurface are provided with said outside electrode terminals; saidthrough-type electrodes or said post electrodes in the lower surface ofsaid second semiconductor device are electrically connected with saidpost electrodes or said through-type electrodes in the upper surface ofsaid first semiconductor device through joints.
 2. The stackedsemiconductor device according to claim 1 having a third semiconductordevice stacked and secured between said first semiconductor device andsaid second semiconductor device over one to a plurality of steps,characterized in that: said third semiconductor device has: asemiconductor substrate; multilayer wiring part including a plurality ofcircuit elements formed at a first main surface side of saidsemiconductor substrate and wiring connected with said circuit elements;a first insulating layer for covering said multilayer wiring part; asecond insulating layer for covering a second main surface to become anopposite face against the first main surface of said semiconductorsubstrate; a plurality of post electrodes formed on respective specifiedwiring of said multilayer wiring part to be exposed in a surface of saidfirst insulating layer; a plurality of through-type electrodes providedto pierce through said semiconductor substrate and said secondinsulating layer from specified depth of said multilayer wiring part,brought into contact to said semiconductor substrate through aninsulating film and connected with specified wiring of said multilayerwiring part respectively, and the post electrodes or the through-typeelectrodes on the upper/lower surfaces of said third semiconductordevice are electrically connected with the post electrodes orthrough-type electrodes of the semiconductor device at the upper stageside and the semiconductor device at the lower stage side throughjoints.
 3. The stacked semiconductor device according to claim 1,characterized in that said semiconductor devices at the respectivestages will become a single body and the respective semiconductordevices overlap each other in corresponding fashion in a same size. 4.The stacked semiconductor device according to claim 1, characterized inthat a plurality of second semiconductor devices smaller than said firstsemiconductor device are disposed and secured in parallel on said firstsemiconductor device.
 5. The stacked semiconductor device according toclaim 1, characterized in that the respective through-type electrodes orthe respective post electrodes on the upper surface of said firstsemiconductor device and the respective through-type electrodes or therespective post electrodes on the lower surface of said secondsemiconductor device are brought into correspondence and areelectrically connected respectively through said joints.
 6. The stackedsemiconductor device according to claim 1, characterized in that saidjoints are not used for joining the respective through-type electrodesor the respective post electrodes on the upper surface of said firstsemiconductor device with the respective through-type electrodes or therespective post electrodes on the lower surface of said secondsemiconductor device but, said post electrodes or said through-typeelectrodes engaged in said joining of said one semiconductor deviceprotrude and those protruding portions are connected to said postelectrodes or said through-type electrodes of the facing semiconductordevice with metal joining.
 7. The stacked semiconductor device accordingto claim 1, characterized in that said post electrodes are formed of aplating film, stud bump electrodes or a CVD film.
 8. The stackedsemiconductor device according to claim 1, characterized in that a metalplate having insulating holes is present between said firstsemiconductor device and said second semiconductor device, in theportion of said insulating holes, said through-type electrodes or saidpost electrodes on the upper surface of said first semiconductor deviceare electrically connected with said through-type electrodes or saidpost electrodes on the lower surface of said second semiconductor devicethrough said joints in a state without contacting said metal plate, saidthrough-type electrodes and said post electrodes of said firstsemiconductor device and said second semiconductor device to face saidmetal plate are electrically connected with said metal plate throughsaid joints.
 9. The stacked semiconductor device according to claim 8,characterized in that said through-type electrodes or said postelectrodes to be given power supply potential of said semiconductordevice or ground potential are connected with said metal plate.
 10. Thestacked semiconductor device according to claim 1, characterized in thatout of said first and second semiconductor devices, said semiconductorsubstrate of one semiconductor device is a silicon substrate and saidsemiconductor substrate of the other semiconductor device is a compoundsemiconductor substrate.
 11. The stacked semiconductor device accordingto claim 1, characterized in that said through-type electrodes and saidpost electrodes are formed of copper, tungsten, titanium, nickel,aluminum or alloy thereof.
 12. The stacked semiconductor deviceaccording to claim 1, characterized in that gap between said firstsemiconductor device and said second semiconductor device is filled withinsulating resin.
 13. The stacked semiconductor device according toclaim 1, characterized in that said second semiconductor device has,likewise said first semiconductor device, a plurality of post electrodesexposed in a surface of said first insulating layer and a plurality ofthrough-type electrodes exposed in a surface of said second insulatinglayer, and through-type electrodes are formed at exposed ends ofspecified said post electrodes or said through-type electrodes locatedin the upper surface.
 14. The stacked semiconductor device according toclaim 1, characterized in that said post electrodes are larger than saidthrough-type electrodes in diameter.
 15. The stacked semiconductordevice according to claim 1, characterized in that said circuit elementsare active elements and passive elements.
 16. The stacked semiconductordevice according to claim 1, characterized in that said semiconductorsubstrates of said respective semiconductor devices have thickness ofaround 5 to 50 μm and said first insulating layer has thickness ofaround 20 to 100 μm.
 17. A semiconductor device characterized by having:a semiconductor substrate; a multilayer wiring part including aplurality of circuit elements formed at a first main surface side ofsaid semiconductor substrate and wiring connected with said circuitelements; a first insulating layer for covering said multilayer wiringpart; a second insulating layer for covering a second main surface tobecome an opposite face against the first main surface of saidsemiconductor substrate; a plurality of post electrodes formed onrespective specified wiring of said multilayer wiring part to be exposedin a surface of said first insulating layer; a plurality of through-typeelectrodes provided to pierce through said semiconductor substrate andsaid second insulating layer from specified depth of said multilayerwiring part, brought into contact to said semiconductor substratethrough an insulating film and connected with specified wiring of saidmultilayer wiring part respectively.
 18. The semiconductor deviceaccording to claim 17, characterized in that protruding electrodes areformed at exposed ends of specified said post electrodes and saidthrough-type electrodes.
 19. The semiconductor device according to claim17, characterized in that said post electrodes are larger than saidthrough-type electrodes in diameter.
 20. The semiconductor deviceaccording to claim 17, characterized in that said post electrodes areformed by a plating film, stud bump electrodes or a CVD film.
 21. Thesemiconductor device according to claim 17, characterized in that saidthrough-type electrodes and said post electrodes are formed of copper,tungsten, titanium, nickel, aluminum or alloy thereof.
 22. Thesemiconductor device according to claim 17, characterized in that saidcircuit elements are active elements and passive elements.
 23. Thesemiconductor device according to claim 17, characterized in that saidsemiconductor substrates of said respective semiconductor devices havethickness of around 5 to 50 μm and said first insulating layer hasthickness of around 20 to 100 μm.
 24. A process for fabricating astacked semiconductor device having a first semiconductor device havingoutside electrode terminals on its lower surface and a secondsemiconductor device stacked and secured on said first semiconductordevice and said both semiconductor devices being brought into electricalconnection, having: (a) a step of aligning, disposing and forming aplurality of product forming parts inclusive of specified circuitelements on a first main surface of a semiconductor substrate; (b) astep of forming a multilayer wiring part in said respective productforming parts by laminating and forming sequentially in a specifiedpattern wiring and insulating layers being connected electrically withsaid circuit elements; (c) a step of forming, at the stage for formingsaid multilayer wiring part, a plurality of holes toward a second mainsurface to become an opposite face against said first main surface ofsaid semiconductor substrate from specified depth of said multilayerwiring part having an insulating film on their surfaces and of formingfilling electrodes to fill those holes with conductive substance and beelectrically connected with specified wiring of said multilayer wiringpart; (d) a step of forming post electrodes on respectively specifiedwiring of said multilayer wiring part; (e) a step of forming, on thefirst main surface of said semiconductor substrate, a first insulatinglayer to cover said post electrodes; (f) a step of removing the surfaceof said first insulating layer by specified thickness to expose saidpost electrodes; (g) a step of removing the second main surface of saidsemiconductor substrate from its surface by specified thickness toexpose said filling electrodes to form through-type electrodes; (h) astep of removing by etching the second main surface of saidsemiconductor substrate by specified thickness to cause saidthrough-type electrodes to protrude by specified length; (i) a step offorming a second insulating layer of specified thickness on the secondmain surface of said semiconductor substrate in a state of exposingforward ends of said through-type electrodes; (j) a step of cutting thesaid semiconductor substrate inclusive of said first and secondinsulating layers in a lattice pattern to divide said respective productforming parts; and (k) a step of forming protruding electrodes atspecified exposed ends among said through-type electrodes and said postelectrodes after said step (i) or after said step (j), wherein throughsaid step (a) to step (k), said first semiconductor device is formed;through selection of said step (a) to step (k), said secondsemiconductor device having, at least, said through-type electrodes orsaid post electrodes is formed; next, said first semiconductor device isdisposed so that said through-type electrodes or said post electrodescome to the lower surface to be regarded as said outside electrodeterminals, and thereafter, said through-type electrodes or said postelectrodes in the lower surface of said second semiconductor device andsaid through-type electrodes or said post electrodes in the uppersurface of said first semiconductor device are brought into electricalconnection with temporary melting treatment applied to said protrudingelectrodes to fabricate a stacked semiconductor device.
 25. The processfor fabricating a stacked semiconductor device according to claim 24,characterized in that said second semiconductor device having only saidthrough-type electrodes is formed through: a step of aligning, disposingand forming a plurality of product forming parts inclusive of specifiedcircuit elements on a first main surface of said semiconductorsubstrate; a step of forming a multilayer wiring part in said respectiveproduct forming parts by laminating and forming sequentially in aspecified pattern wiring and insulating layers being connectedelectrically with said circuit elements; a step of forming, at the stagefor forming said multilayer wiring part, a plurality of holes toward asecond main surface to become an opposite face against said first mainsurface of said semiconductor substrate from specified depth of saidmultilayer wiring part having an insulating film on their surfaces andof forming filling electrodes to fill those holes with conductivesubstance and be electrically connected with specified wiring of saidmultilayer wiring part; a step of forming a first insulating layer onthe first main surface of said semiconductor substrate; a step ofremoving the second main surface of said semiconductor substrate fromits surface by specified thickness to expose said filling electrodes toform through-type electrodes; a step of removing by etching the secondmain surface of said semiconductor substrate by specified thickness tocause said through-type electrodes to protrude by specified length; astep of forming a second insulating layer of specified thickness on thesecond main surface of said semiconductor substrate in a state ofexposing forward ends of said through-type electrodes; a step of formingprotruding electrodes at exposed portions of said through-typeelectrodes; and a step of cutting said semiconductor substrate inclusiveof said first and second insulating layers in a lattice pattern todivide said respective product forming parts.
 26. The process forfabricating a stacked semiconductor device according to claim 24,characterized in that said second semiconductor device having only saidpost electrodes is formed through: a step of aligning, disposing andforming a plurality of product forming parts inclusive of specifiedcircuit elements on a first main surface of a semiconductor substrate; astep of forming a multilayer wiring part in said respective productforming parts by laminating and forming sequentially in a specifiedpattern wiring and insulating layers being connected electrically withsaid circuit elements; a step of forming post electrodes on respectivelyspecified wiring of said multilayer wiring part; a step of forming, onthe first main surface of said semiconductor substrate, a firstinsulating layer to cover said post electrodes; a step of removing thesurface of said first insulating layer by specified thickness to exposesaid post electrodes; a step of removing the second main surface of saidsemiconductor substrate from its surface by specified thickness to makesaid semiconductor substrate thin; a step of forming a second insulatinglayer of specified thickness on the second main surface of saidsemiconductor substrate; a step of forming protruding electrodes atexposed portions of said post electrodes; and a step of cutting saidsemiconductor substrate inclusive of said first and second insulatinglayers in a lattice pattern to divide said respective product formingparts.
 27. The process for fabricating a stacked semiconductor deviceaccording to claim 24, characterized by: having a step of stacking andsecuring one to a plurality of third semiconductor device (devices)stacked and secured between said first semiconductor device and saidsecond semiconductor device through said step (a) to step (k); formingfilling electrodes provided on one surface of said third semiconductordevice so as to correspond with the filling electrodes or the postelectrodes of the facing semiconductor device; and forming postelectrodes provided on the other surface of said third semiconductordevice so as to correspond with the filling electrodes or the postelectrodes of the facing semiconductor device.
 28. The process forfabricating a stacked semiconductor device according to claim 24,characterized in that a plurality of second semiconductor devicessmaller than said first semiconductor device are disposed and secured inparallel on said first semiconductor device.
 29. The process forfabricating a stacked semiconductor device according to claim 24,characterized in that the respective filling electrodes or respectivepost electrodes on the upper surface of said first semiconductor deviceare formed so as to correspond with the respective filling electrodes orrespective post electrodes on the lower surface of said secondsemiconductor device.
 30. The process for fabricating a stackedsemiconductor device according to claim 24, characterized in that: insaid step (e), at the time of forming said first insulating layer, resinhardening processing is set to insufficient primary hardeningprocessing; in said step (f), after exposing said post electrodes on thesurface of said first insulating layer, secondary hardening processingaccompanying hardening contraction of said first insulating layer isimplemented to expose forward ends of said post electrodes on thesurface of said first insulating layer; at the time when said secondsemiconductor device is stacked and secured onto said firstsemiconductor device, ultrasonic oscillation is applied to theprotruding portions of said post electrodes to be brought intoconnection with facing said filling electrodes or said post electrodesby metal joint.
 31. The process for fabricating a stacked semiconductordevice according to claim 24, characterized by forming said postelectrodes with a plating film, stud bump electrodes or a CVD film. 32.The process for fabricating a stacked semiconductor device according toclaim 24, characterized by: interposing a metal plate having insulatingholes between said first semiconductor device and said secondsemiconductor device, in the portion of said insulating holes,electrically connecting said filling electrodes or said post electrodeson the upper surface of said first semiconductor device with saidfilling electrodes or said post electrodes on the lower surface of saidsecond semiconductor device with temporary melting treatment applied tosaid protruding electrodes, and electrically connecting saidthrough-type electrodes and said post electrodes of the firstsemiconductor device and said second semiconductor device to face saidmetal plate with said metal plate with temporary melting treatmentapplied to said protruding electrodes.
 33. The process for fabricating astacked semiconductor device according to claim 32, characterized byconnecting said filling electrodes or said post electrodes to be givenpower supply potential of said semiconductor device or ground potentialwith said metal plate.
 34. The process for fabricating a stackedsemiconductor device according to claim 24, characterized by filling agap between said first semiconductor device and said secondsemiconductor device with insulating resin to harden it.
 35. The processfor fabricating a stacked semiconductor device according to claim 24,characterized by using a silicon substrate as said semiconductorsubstrate for one semiconductor device out of said first and secondsemiconductor devices to form said circuit elements and using a compoundsemiconductor substrate as said semiconductor substrate for the othersemiconductor device to form said circuit elements.
 36. The process forfabricating a stacked semiconductor device according to claim 24,characterized by, in fabricating said second semiconductor device,likewise said first semiconductor device, forming a plurality of postelectrodes exposed in a surface of said first insulating layer and aplurality of through-type electrodes exposed in a surface of said secondinsulating layer, and providing protruding electrodes to exposed ends ofspecified said post electrodes or said through-type electrodes to becomethe upper surface.
 37. The process for fabricating a stackedsemiconductor device according to claim 24, characterized by formingsaid post electrodes larger than said through-type electrodes indiameter.
 38. The process for fabricating a stacked semiconductor deviceaccording to claim 24, characterized by forming active elements andpassive elements as said circuit elements.
 39. The process forfabricating a stacked semiconductor device according to claim 24,characterized by in said step (e), forming said first insulating layerto have thickness of around 20 to 100 μm; in said step (c), forming saidholes to have depth of around 5 to 50 μm; in said step (f), forming saidpost electrodes to have thickness of around 20 to 100 μm; and in saidstep (g), forming said through-type electrodes to have thickness ofaround 5 to 50 μm.
 40. A process for fabricating a semiconductor device,characterized by having: (a) a step of aligning, disposing and forming aplurality of product forming parts inclusive of specified circuitelements on a first main surface of a semiconductor substrate; (b) astep of forming a multilayer wiring part in said respective produceforming parts by laminating and forming sequentially in a specifiedpattern wiring and insulating layers being connected electrically withsaid circuit elements; (c) a step of forming, at the stage for formingsaid multilayer wiring part, a plurality of holes toward a second mainsurface to become an opposite face against said first main surface ofsaid semiconductor substrate from specified depth of said multilayerwiring part having an insulating film on their surfaces and of formingfilling electrodes to fill those holes with conductive substance and beelectrically connected with specified wiring of said multilayer wiringpart; (d) a step of forming post electrodes on respectively specifiedwiring of said multilayer wiring part; (e) a step of forming, on thefirst main surface of said semiconductor substrate, a first insulatinglayer to cover said post electrodes; (f) a step of removing the surfaceof said first insulating layer by specified thickness to expose saidpost electrodes; (g) a step of removing the second main surface of saidsemiconductor substrate from its surface by specified thickness toexpose said filling electrodes to form through-type electrodes; (h) astep of removing by etching the second main surface of saidsemiconductor substrate by specified thickness to cause saidthrough-type electrodes to protrude by specified length; (i) a step offorming a second insulating layer of specified thickness on the secondmain surface of said semiconductor substrate to expose forward ends ofsaid through-type electrodes; and (j) a step of cutting the saidsemiconductor substrate inclusive of said first and second insulatinglayers in a lattice pattern to divide said respective product formingparts.
 41. The process for fabricating a semiconductor device accordingto claim 40, characterized in that: in said step (e), at the time offorming said first insulating layer, resin hardening processing is setto insufficient primary hardening processing; and in said step (f),after exposing said post electrodes on the surface of said firstinsulating layer, secondary hardening processing accompanying hardeningcontraction of said first insulating layer is implemented to exposeforward ends of said post electrodes on the surface of said firstinsulating layer.
 42. The process for fabricating a semiconductor deviceaccording to claim 40, characterized by forming protruding electrodes atspecified exposed portions of said through-type electrodes and said postelectrodes after said step (i) or after said step (j).
 43. The processfor fabricating a semiconductor device according to claim 40,characterized by forming said post electrodes larger than saidthrough-type electrodes in diameter.
 44. The process for fabricating asemiconductor device according to claim 40, characterized by formingsaid post electrodes with a plating film, stud bump electrodes or a CVDfilm.
 45. The process for fabricating a semiconductor device accordingto claim 40, characterized in that said circuit elements are activeelements and passive elements.
 46. The process for fabricating asemiconductor device according to claim 40, characterized by in saidstep (e), forming said first insulating layer to have thickness ofaround 20 to 100 μm; in said step (c), forming said holes to have depthof around 5 to 50 μm; in said step (f), forming said post electrodes tohave thickness of around 20 to 100 μm; and in said step (g), formingsaid through-type electrodes to have thickness of around 5 to 50 μm.